MODIFYING INSTRUCTION SETS IN THE GEM5 SIMULATOR TO SUPPORT FAULT TOLERANT DESIGNS

SEPTEMBER 2015

CHUAN ZHANG B.S.,

BEIJING INSTITUTE OF TECHNOLOGY M.S.M.E.,

UNIVERSITY OF MASSACHUSETTS AMHERST

Directed by: Professor Israel Koren

Traditional fault tolerant techniques such as hardware or time redundancy incur high overhead and are inefficient for checking arithmetic operations. Our objective is to study an alternative approach of adding new instructions to check arithmetic operations. These checking instructions either rely on error detecting code or calculate approximate results and consequently, consume much less execution time. To evaluate the effectiveness of such an approach we wish to modify several benchmarks to use checking instructions and run simulation experiments to find out their execution time and memory usage. However, the checking instructions are not included in the instruction set and as a result, are not supported by current architecture simulators. Therefore, another objective of this thesis is to develop a method for inserting new instructions in the Gem5 simulator and cross compiler. The insertion process is integrated into a software tool called Gtool. Gtool can add an error checking capability to C programs by using the new instructions.

You can find the thesis here