[gem5-users] Adding CommMonitor between CPU and L1d-cache

CommMonitor L1-dcache and CPU

I want to add the CommMonitor between CPU and L1d-cache in SE mode to trace
all the memory operation requests in the system. I am running in x-86 SE
mode

I added following lines in the /src/cpu/BaseCPU.py file

system.monitor3 = CommMonitor(trace_file="CT_mon3.txt")
MasterPort("Data Port") = system.monitor3.master
system.monitor3.slave = dcache_port

and commented the following line
dcache_port = MasterPort("Data Port")

The code executes but the trace file does not get generated. The
CommMonitor3 also does not get recorded in config.ini.

How to generate this trace? Any alternate ideas that I can try.