The research focus of the Mixed-Signal Integrated Circuits and Systems (MICS) lab is on low power integrated circuits and systems targeted to high speed interconnects for wireline and wireless communications, sensing, signal acquisition and processing. Our research interests intersect with device physics, systems modeling and design, machine learning and hardware security.

There is an opening for Ph.D. applicants with strong background in analog/mixed-signal circuit design. Familiarity with silicon prototyping from schematic capture through tape-out is a plus. Interested applicants should email me their CVs and indicate their interest to work with the Mixed-Signal Integrated Circuits and Systems (MICS) Lab in their application.

Open Research Projects:

Low complexity transceiver architectures for multi-Gb/s I/O

With the steep increase in aggregate I/O bandwidth demands, higher per lane bandwidths are required over existing channels. The resulting increase in channel loss can be overcome in multiple ways; all of which lead to more equalization complexity. In past projects, innovative timing recovery schemes where used to drive simpler equalizers at the receiver. In this research thrust, we investigate new transceiver architectures that enable enhanced equalization without increase in complexity over a wide range of applications and use cases.

High efficiency analog-to-digital converters for digital receivers

Digital receiver equalizers have become the go to equalization architectures for high loss channels. One of the reasons is that they avoid the trade-off between number of DFE taps and data rate. Another reasons are that they enable multi-standard use of the hardware due to their high programmability and that the digital designs can be ported easily from technology to another. However, current designs still lag their mixed-mode counterparts in power and area efficiency. A major cause of this power efficiency gap is the complexity of the analog-to-digital converter (ADC) in the front-end. In this project, we combine our extensive prior work on ADCs with serial I/O system expertise to explore new digital receiver topologies that yield higher area and power efficiencies.

Robust timing recovery for multi-level signaling

Clock and data recovery (CDR) schemes in serial I/Os rely on phase detectors (PD) that come in several flavors, but they can all be grouped under oversampled baud rate phase detectors. Both of these PD schemes add to receiver complexity because of the need for additional slicers and extra clock phases in the case of oversampled PDs. This added complexity only increases in the case of multi-level signaling, like PAM 4 or higher order PAM. Additionally, there is increased uncertainty in the lock point due to multiple zero-crossings in the PAM N eyes. While oversampled PD offer the ability to use transition filtering to mitigate the lock point uncertainties, they may not be feasible in high data rate applications. For this research thrust, we will be investigating CDR techniques and timing functions that enable robust timing recovery with minimal receiver overhead.