Publications

Journal Papers 

  1. T. Musah and A. Namachivayam, “Robust Timing Error Detection for Multilevel Baud-Rate CDR,”  IEEE Trans. Circuits Syst. I (TCAS1), accepted.
  2. A. Abdelaziz and T. Musah, “A time latch for high speed time-based ADCs,” Electron. Lett.(EL), vol. 58, pp.542-544, https://doi.org/10.1049/ell2.12535, 2022.
  3. T. Musah, J. E. Jaussi, G. Balamurugan, S. Hyvonen, T.-C. Hsueh, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, B. Casper, “A 4-32Gb/s Bidirectional Link with 3-tap FFE/6-tap DFE and Collaborative CDR in 22nm CMOS,” IEEE J. Solid-State Circuits (JSSC), vol. 49, no. 12, pp. 3079-3090, Dec. 2014.
  4. T. Musah and U. Moon, “Correlated level shifting integrator with reduced sensitivity to amplifier gain,”
    Electron. Lett. (EL), vol. 47, no. 2, pp. 91-92, Jan. 29, 2011.
  5. Y. Hu, N, Maghari, T. Musah, and U. Moon, “Time-interleaved noise-shaping integrating quantisers,”
    Electron. Lett. (EL), vol. 46, no. 11, pp. 757-758, May 27, 2010.
  6. O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aniya, K. Hamashita, and U. Moon, “Design of a 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC,” IEEE J. Solid-State Circuits (JSSC), vol. 45, no. 4, pp. 719-730, Apr. 2010.
  7. T. Musah and U. Moon, “Correlated level shifting technique with cross-coupled gain-enhancement
    capacitors,” Electron. Lett. (EL), vol. 45, no. 13, pp. 672-674, Jun. 18, 2009.
  8. T. Musah, B.R. Gregoire, E. Naviasky, and U. Moon, “Parallel correlated double sampling technique for pipelined analogue-to-digital converters,” Electron. Lett. (EL), vol. 43, no. 23, Nov. 8, 2007.

Conference Papers

  1. M. Ahmed and T. Musah, “Characterization of Sub-Nyquist TIA with Equalization in Optical Receivers,” in IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2037-2041, May 2022.
  2. M. Abouzeid and T. Musah, “Hysteretic Error Extraction in Multi-Level Wireline Receivers,” in IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1-5, May 2021.
  3. A. AbdelAziz and T. Musah, “The Effect of Equalization on Nonlinearity in Time-Based Decision Feedback Equalizers,” in IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1-5, May 2021.
  4. T. Musah, “Time-Based Error Extraction for Multilevel Receivers,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1-5, Oct. 2020.
  5. J. E. Jaussi, G. Balamurugan, S. Hyvonen, T.-C. Hsueh, T. Musah, G. Keskin, S. Shekhar, J. Kennedy, S. Sen, R. Inti, M. Mansuri, M. Leddige, B. Horine, C. Roberts, R. Mooney, B. Casper, “A 205mW 32Gb/s 3-Tap FFE/6-Tap DFE Bi-directional Serial Link in 22nm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 440-441, Feb. 2014.
  6. T.-C. Hsueh, G. Balamurugan, J. Jaussi, S. Hyvonen, J. Kennedy, G. Keskin, T. Musah, S. Shekhar, R. Inti, S. Sen, M. Mansuri, C. Roberts, B. Casper, “A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS,” IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 444-445, Feb. 2014.
  7. B. Hershberg, T. Musah, S. Weaver, and U. Moon, “The effect of correlated level shifting on noise performance in switched capacitor circuits,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 942-945, May 2012.
  8. B.R. Gregoire, T. Musah, N. Maghari, S. Weaver, and U. Moon, “A 30% beyond Vdd signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp,” IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 345-348, Nov. 2011.
  9. O. Rajaee, Y. Hu, M. Gande, T. Musah, and U. Moon, “An interstage correlated double sampling technique for switched-capacitor gain stages,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1252-1255, May 2010.
  10. T. Musah and U. Moon, “Pseudo-differential zero-crossing-based circuits with differential
    error suppression    ,” IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1731-1734, May 2010.
  11. T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U. Moon, “A 630uW zero-crossing-based delta-sigma ADC using switched-resistor current sources in 45nm CMOS,” IEEE Custom Int. Circuits Conf. (CICC), pp. 1-4, Sep. 2009.
  12. O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu, and U. Moon, “A 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC,” IEEE Symp. VLSI Circuits (VLSI), pp. 74-75, Jun. 2009.
  13. S. Chatterjee, T. Musah, Y. Tsividis, and P. Kinget, “Weak inversion MOS varactors for 0.5 V analog integrated filters,” IEEE Symp. VLSI Circuits (VLSI), Jun. 2005, pp. 272-275.

Graduate Thesis

  1. Tawfiq Musah, “Low power design techniques for analog-to-digital converters in submicron CMOS,” Ph.D. Dissertation, Oregon State University, 2010.

Patents

  1. E. Alpman, A. Amadjikpe, O. Asaf, K. Azadet, R. Banin, M. Baryakh, A. Bazov, S. Brenna, B. Casper, A. Chakrabarti, G. Chance, D. Choudhury, E. Cohen, C. Da Silva, S. Dalmia, S. Daneshgar Asl, K. Dasgupta, K. Datta, B. Davis, O. Degani, A. M Fahim, A. Freiman, M. Genossar, E. Gerson, E. Goldberger, E. Gordon, M. Gordon, J. Hagn, S. Kang, T.  Kao, N. Kogan, M. Komulainen, I. Kushnir, S. Lahti, M. Lampinen, N. Landsberg, W. Lee, R. Levinger, A. Molina, R. Moreno, T. Musah, N. Narevsky, H. Nikopour, O. Orhan, G. Palaskas, S. Pellerano, R. Pongratz, A. Ravi, S. Ravid, P. Sagazio, E. Sasoglu, L. Shakedd, G. Shor, B. Singh, M. Soffer, S. Talwar, N. Tanzi, M. Teplitsky, C. Thakkar, J. Thakur, A. Tsarfati, Y.Tsfati, M. Verhelst, N. Weisman, S. Yamada, A. Yepes, D. Kitchir, “Wireless communication technology, apparatuses, and methods,” US Patent Number: 11424539, Aug. 2022.
  2. T. Musah, H. Venktramam, B. Casper, “Low power high speed receiver with reduced decision feedback equalizer samplers,” US Patent Number: 10756931, Aug. 2020.
  3. J. P. Kulkarni, A. Ravi, D. Somasekhar, G. Balamurugan, S. Shekhar, T. Musah, T.-C. Hsueh, “Digitally trimmable integrated resistors including resistive memory elements,” US Patent Number: 10347309, Jul. 2019
  4. T. Musah, H. Venktramam, B. Casper, “Low power high speed receiver with reduced decision feedback equalizer samplers,” US Patent Number: 10341145, Jul. 2019.
  5. T. Musah, G. Keskin, G. Balamurugan, J. E. Jaussi, and B. Casper, “Wireline receiver circuitry having collaborative timing recovery,” US Patent Number: 9794089, Oct. 2017.
  6. J. P. Kulkarni, A. Ravi, D. Somasekhar, G. Balamurugan, S. Shekhar, T. Musah, T.-C. Hsueh, “Digitally trimmable integrated resistors including resistive memory elements,” US Patent Number: 9589615, Mar. 2017.
  7. H. Venkatram, S. Hyvonen, T. Musah, and B. Casper, “High speed receiver with one-hot decision feedback equalizer,” US Patent Number: 9537682, Jan. 2017.
  8. T. Musah, G. Keskin, G. Balamurugan, J. E. Jaussi, and B. Casper, “Wireline receiver circuitry having collaborative timing recovery,” US Patent Number: 9374250, Jun. 2016.